I2C / I2S - PHY (HARD IP)
Dolphin Technology's hardened I2C PHY and I2S PHY provides a complete physical interface between bus and core logic to make a device I2C/I2S compliant. It is fully compliant with the I2C and I2S specifications.
The following TSMC process nodes are supported:
16nm FF+, FFC
28nm HP, HPx, LP, ULP
40nm G, LP, ULP
55nm GP, LP, ULP, EF
65nm GP, LP
I2C / I2S CONTROLLER (SOFT IP)
Dolphin's I2C controller and I2S controller is designed to quickly and easily integrate into any SoC, and is optimized to provide a complete solution when combined with Dolphin's I2C/I2S PHY IP.
It is designed for 0.85/1.05 core VDD and 1.8V VDDO with support for Standard-mode, Fast-mode, Fast-mode Plus, and High Speed bus protocols. This is a fail-safe IO (VDDO can be powered down) and can tolerate 1.8V at the pad.
Dolphin’s I2C/I2S Controllers support all TSMC process nodes.