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40,55,65nm Memory (HPC+, HPC, HPM, HPL, HP, LP, and ULP)


Single and Dual Port SRAM with both Row and Column redundancy with Following Low Power options:

  • Low Leakage with retention (light and deep sleep)

  • Power Gating with retention and without retention

  • Dual Rail (SRAM Periphery at lower Voltage)

  • Combinations of above low power options

1-Port and 2-port Register File with Column redundancy and all the above Low power options

Pseudo 2-Port Register Files Compiler

Multi-Banking Single Port SRAM compiler for larger SRAMs

ROM Compiler


Low Power Register Files Tiles to created low leakage memory blocks

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